1. Field of the Invention
The present invention relates to circuit boards and methods for fabricating the same, and more particularly, to a circuit board with a wiring layer bonded to a surface of the circuit board by a material with high bonding strength.
2. Description of the Prior Art
To enhance precision of the circuit layout of circuit boards for use in semiconductor chip packaging, a build-up technique has been developed, which involves stacking a plurality of dielectric layers and wiring layers on a core circuit board, and forming a plurality of plated through holes (PTHs) in the core circuit board, wherein the PTHs are conductive to circuits on upper and lower surfaces of the core circuit board. FIGS. 1A to IN show a conventional method for fabricating the core circuit board.
Referring to FIG. 1A, a core board 10 in the form of a copper coated laminate (CCL) is provided. A first metal layer 11a, which is made of copper and has good electrical conductivity, is formed on at least one surface of the core board 10.
Referring to FIG. 1B, a thinning step is performed on the first metal layer 11a by a chemical or physical technique as appropriate, so as to form a first thinned metal layer 11a′. 
Referring to FIG. 1C, a first conductive layer 12a is formed on the thinned metal layer 11′. 
Referring to FIG. 1D, a first plated metal layer 11b is plated to and formed on the first conductive layer 12a. 
Referring to FIG. 1E, a first resist layer 13a is formed on the first plated metal layer 11b, and a plurality of first openings 131a are formed in the first resist layer 13a to expose a portion of the first plated metal layer 11b. 
Referring to FIG. 1F, portions of the first plated metal layer 11b, the first conductive layer 12a, and the first thinned metal layer 11a′, which are not covered by the first resist layer 13a, are removed, so as to form a first wiring layer 14a on the core board 10.
Referring to FIG. 1G, the first resist layer 13a is removed, so as to expose the first wiring layer 14a. 
Referring to FIG. 1H, a second metal layer 11c with a lower surface thereof being covered by a dielectric layer 141 is formed on the core board 10 and the first wiring layer 14a, wherein the dielectric layer 141 is a prepreg.
Referring to FIG. 1I, the second metal layer 11c is thinned so as to form a second thinned metal layer 11c′. 
Referring to FIG. 1J, a plurality of openings 1410 are formed in the second thinned metal layer 11c′ and the dielectric layer 141 so as to expose a portion of the first wiring layer 14a. 
Referring to FIG. 1K, a second conductive layer 12b is formed on the second thinned metal layer 11c′, the surface of the openings 1410, and the exposed portion of the first wiring layer 14a. Then, a second resist layer 13b is formed on the second conductive layer 12b, wherein a plurality of second openings 132b are formed in the second resist layer 13b such that the second openings 132b correspond in position to and expose the openings 1410 of the dielectric layer 141 and a portion of the second conductive layer 12b. 
Referring to FIG. 1L, a second wiring layer 14b is plated into the second openings 132b of the second resist layer 13b via the second conductive layer 12b, and a plurality of conductive vias 142 are plated into the openings 1410 of the dielectric layer 141 such that the conductive vias 142 are electrically connected to the first wiring layer 14a. 
Referring to FIG. 1M, the second resist layer 13b and the second conductive layer 12b thereunder are removed so as to expose the second wiring layer 14b. 
Referring to FIG. 1N, the steps depicted in FIGS. 1H to 1M can be repeated, so as to form a circuit build-up structure 14. The circuit build-up structure 14 comprises the dielectric layer 141, the second wiring layer 14b superimposed on the dielectric layer 141, and the conductive vias 142 formed in the dielectric layer 141 and electrically connected to the second wiring layer 14b. The circuit build-up structure 14 further comprises a plurality of electrically connecting pads 143 conductive to the second wiring layer 14b. An insulated protection layer 15A, such as a solder mask, is formed on the circuit build-up structure 14. A plurality of openings 150 is formed in the insulated protection layer 15. The openings 150 correspond in position to and expose the electrically connecting pads 143.
The core board 10 and the dielectric layer 141 are made of insulating material. The first, second and third metal layers 11a, 11b, 11c are made of metallic material. Metallic material can be bonded to non-metal material but hardly firmly. Hence, the core board 10 is unlikely to be bonded to the first wiring layer 14a firmly, and the dielectric layer 141 is unlikely to be bonded to the second wiring layer 14b firmly, thereby leading to peel or delamination in a subsequent process readily.
In the event of a fine-pitch circuit, the circuit pitch of the first and second wiring layers 14a, 14b is much less, which further deteriorates the bonding between the first wiring layer 14a and the core board 10 or the bonding between the second wiring layer 14b and the dielectric layer 141, thereby increasing the likelihood of peeling or delamination of the first and second wiring layers 14a, 14b in a subsequent process.
Therefore, the problem to be solved here is to provide a technique for fabricating a circuit board, which can enhance the bonding between a wiring layer made of metallic material and a dielectric layer or core board made of non-metallic material so as to prevent peeling or delamination, reduce the thickness of the metal layer, and facilitate formation of a fine-pitch wiring layer.